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Product Details:
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| Number Of Channels: | 2 | Frequency Range：: | 3MHz-6GHz |
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| Bandwidth:: | 200MHz Per Channel | Feature:: | Dual-core ARM Cortex-A9 800 MHz CPU |
| FPGA:: | Xilinx Zynq-7100 SoC | DAC:: | 14-bit |
| High Light: | 200MHz ettus usrp SDR,ettus usrp SDR 200MHz,ettus usrp SDR real time 200MHz |
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Universal Software Radio Peripheral USRP-LW N321
Product Overview
USRP-LW N321 is a network SDR that provides reliability and fault tolerance for deployment in large-scale and distributed wireless systems. This is a high-performance SDR that provides 2 RX and 2 TX channels in a half-width RU size. Each channel can provide up to 200 MHz instantaneous bandwidth and cover an extended frequency range from 3 MHz to 6 GHz. The baseband processor uses Xilinx Zynq-7100 SoC to deliver a large user-programmable FPGA. It has two SPF+ ports and one QSFP+ port, supports 1 GbE, 10 GbE and Aurora interfaces, and can stream high-throughput IQ to the host PC or FPGA coprocessor. The flexible synchronization architecture supports 10 MHz clock reference, PPS time reference, external TX and RX LO input and GPSDO, which can realize phase coherent MIMO test platform.
Main Features
1.Reliable and fault-tolerant deployment 2.Remote management capabilities 3.Stand-alone (embedded) or host-based (network stream) operation 4.Fully integrated and assembled (USRP N321 does not support exchangeable daughter cards) 5.3 MHz to 6 GHz extended frequency range 6.Up to 200 MHz instantaneous bandwidth per channel 7.2RX,2TX 8.RX,TX Filter bank 9.14-bit ADC, 16-bit DAC 10.Master clock rate:200,245.76250 MS / s 11.Xilinx Zynq-7100 SoC 12.Dual-core ARM Cortex-A9 800 MHz CPU 13.1 QSFP+ port 14.2 SFP+ ports (1 Gigabit Ethernet, 10 Gigabit Ethernet, Aurora) 15.RJ45(1 GbE) 16.Clock reference 17.PPS time reference 18.External RX LO, TX LO input and output ports 19.Built-in GPSDO 20.1 type A USB host port 21.1 micro-USB port (serial console, JTAG) 22.Watchdog timer 23.OpenEmbedded Linux 24.USRP hardware driver (UHD3.15.0.0 or higher) and open source software API version 25.RFNoC™ FPGA Development Framework
Technical index:
| Parameter category | numeric value | unit | Parameter category | numeric value | unit |
| reception | launch | ||||
| Number of channels | 2 | - | Number of channels | 2 | - |
| Gain range | -16 ~ 34 | dB | Gain range | -30 ~ 25 | dB |
| Gain stepping | 1 | dB | Gain stepping | 1 | dB |
| Maximum input power | -15 | dBm | Maximum input power | -15 | dBm |
| Filter bank |
450 ~ 760 760 ~ 1100 1100 ~ 1410 1410 ~ 2050 2050 ~ 3000 3000 ~ 4500 4500 ~ 6000 |
MHz | Filter bank |
450 ~ 650 650 ~ 1000 1000 ~ 1350 1350 ~ 1900 1900 ~ 3000 3000 ~ 4100 4100 ~ 6000 |
MHz |
| An external local oscillator frequency range can be input | 0.45 ~ 6 | GHz | An external local oscillator frequency range can be input | 0.45 ~ 6 | GHz |
| Tuning time | 245 | us | Tuning time | 245 | us |
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TX/RX switching time |
750 | us | TX/RX switching time | 750 | us |
| Conversion and clock performance | power | ||||
| Sample rate | 200,245.76,250 | MS/s | DC voltage input | 12,7 | V,A |
| ADC resolution | 14 | bits | power consumption | 60 ~ 80 | W |
| DAC resolution | 16 | bits | Physical properties | ||
| size | 380×220×45 | mm | |||
| GPSDO frequency stability is not locked | 0.1 | ppm | weight | 3.4 | kg |
| GPSDO PPS relative to UTC accuracy | <8 | ns | Operating environment requirements | ||
| GPSDO latency stability |
<+/-50 3 25 |
us hours °C |
Stable range of operation | 0 ~ 50 | °C |
| Storage temperature range | -40 ~ 70 | °C | |||
Contact Person: Mr. Chen
Tel: 18062514745
