Portable E310 USRP Software Defined Radio 9 Axis Measurement Unit

Software Defined Radio, USRP-LW E310

Product overview:

The USRP E310 offers a portable stand-alone software defined radio platform designed for field deployment. The flexible 2×2 MIMO AD9361 transceiver from Analog Devices provides up to 56 MHz of instantaneous bandwidth and spans frequencies from 70 MHz – 6 GHz to cover multiple bands of interest. RF filter banks in both the transmitter and receiver front-end enhance selectivity.

The baseband processor uses the Xilinx Zynq 7020 SoC to deliver FPGA accelerated computations combined with stand-alone operation enabled by a dual-core ARM CPU. The USRP E310 includes a rich set of peripherals such as an integrated GPS receiver for position awareness and time synchronization, as well as two host USB ports for extending storage, I/O, and communication options with off-the-shelf devices. Users can rapidly prototype and deploy designs for mobile and embedded applications with tight size, weight, and power requirements.

Main feature:

• Frequency coverage 70 MHz-6 GHz
• Up to 56MHz signal bandwidth
• 2x2 MIMO transceiver
• The transceiver link has a preselected filter bank
• Dual-core ARM Cortex A9-886 MHz processor, Xilinx Zynq 7020 SoC FPGA
• 1GB DDR3 RAM for ARM CPUs, 512 MB DDR3 RAM for FPGA Logic
• The sampling rate from FPGA to ARM processor is up to 10MS/s
• Support the use of PPS clock reference synchronization
• Integrated global positioning GPS system receiver
• Built-in 9-axis inertial measurement unit
• 1 Gb Ethernet interface and USB interface
• Size: 133 x 68.2 x 26.4 mm　 Weight: 357 g
• Built-in OpenEmbedded operating system
• Support open source UHD 3.8.0 or newer driver and API interface
• FPGA development framework supporting RFNoC
• Support GNU Radio
• The audio interface on the front panel has been cancelled
• OpenEmbedded Linux
• USRP hardware driver (UHD) open source software API version 14.0 or higher
• RFNoC™ FPGA Development Framework
• Related parameters:

Performance description:

The AD9361 transceiver of the RF front-end provides instantaneous bandwidth up to 56 MHz, the frequency range covers 70 MHz-6 GHz, and supports 2X2 MIMO. The RF preselection filter bank at the front end of the transmit link and the receive link enhances frequency selectivity.

The baseband processor uses Xilinx Zynq 7020 SoC to provide FPGA accelerated computing, combined with the independent operation supported by dual-core ARM CPU. USRP-LW E310 integrates a wealth of peripherals, such as an integrated GPS receiver that can be used for location awareness and time synchronization, and dual USB host ports that can be used for expanded storage space and other I/O devices. Using off-the-shelf equipment, users can quickly prototype and develop embedded applications.

The USRP embedded series uses a Linux distribution customized by the OpenEmbedded framework to meet the specific needs of the application. The default operating system is pre-installed with USRP Hardware Driver™ (UHD) software and third-party development tools such as GNU Radio. E310 also supports RFNoC technology. The RFNoC FPGA development framework can perform real-time calculations and meet the requirements of broadband signal processing.

Operating system and development framework