High Performance, Universal Software Radio Peripheral USRP-LW X310
X310 is a high-performance, scalable SDR platform. The architecture combines two extended-bandwidth daughterboard slots covering 0 – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE, dual 1 GigE), and a large Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 1U form factor.
1. At the heart of the USRP-LW X310, the XC7K410T FPGA provides high-speed connectivity between all major components within the device including radio frontends, host interfaces, and DDR3 memory.
2. The default FPGA core provided with UHD provides all of the functional blocks for digital down-conversion and up-conversion, fine-frequency tuning, and other DSP functions allowing it to be interchangeable with other USRP devices using the UHD architecture.
3. The large Kintex-7 FPGA provides additional space for developers to incorporate custom DSP blocks and is compatible with a large number of USRP supported development frameworks, reference architectures, and open source projects.
|RF performance parameters when paired with SBX-LW 120
|DC voltage input
|Single-sideband signal/image rejection
|Convert module parameters
|ADC sampling rate (max
|DAC sampling rate
|Enter a third-order intercept point
|With host maximum rate (16b).
|Local vibration accuracy
|GPSDO precision is not locked
|Weight (2 sheets SBX-LW 120).
The USRP-LW X310 offers a variety of high speed interfaces to choose from. On the panel of the box, the Gigabit Ethernet port is the easiest way to connect. For applications with extended bandwidth and low latency, such as PHY/MAC research, the LW X310 provides an efficient bus interface PCIe x4 for this deterministic operation. When the application uses network records or multi-node processing, 10G ports are the best choice. The USRP-LW X310 includes many additional features that will help with some other wireless applications. For example, in FPGA design, 1GB DDR3 on the motherboard can be used as data buffering and data storage. The optional internal GPSDO provides a highly accurate frequency reference when synchronized to a GPS system with a synchronization delay of less than 50ns. Allows the user to control external components such as amplifiers and switches through the GPIO interface, supports inputs such as event triggers, and observes debug signals. The USRP-LW X310 also includes an internal JTAG adapter that allows developers to easily load and debug new FPGA images.
System development environment:
Performance comparison between Networked series and X series FPGA:
Included in This Equipment:
1. USRP-LW X310
6. Four SMA-Bulkhead Cables
Test of USRP-LW X310
The test report of X310 and 3 daughterboards(WBX, SBX, UBX)can be viewed in the details of daughterboards