DDR4 64GB Embedded SDR,
3980 Software Defined Radio,
3980 Embedded SDR
Standalone Software Defined Radio SDR-LW 3980
The SDR-LW 3980 is the latest 8-channel high-performance SDR (software defined radio) standalone device launched by Wuhan Luoguang Electronics Co., Ltd. Consists of an on-board processor, an FPGA, and an RF front end. The product has a built-in Intel i9 processor, 512GB SSD, 64GB of RAM. Frequency coverage is from 75 MHz to 6 GHz, with a single channel bandwidth of up to 200 MHz. The FPGA features the resource-rich, user-programmable Xilinx MPSOC ZU11EG. Like all SDR devices, the device has built-in Ubuntu, GNU Radio, etc.
Zynq® UltraScale+ ™ MPSoC devices provide 64-bit processor scalability while combining real-time control with a hardware and software engine for graphics, video, waveform, and packet processing. Based on a general-purpose real-time processor and platform with programmable logic, quad applications processors and GPU (EG) devices, the possibilities for applications such as 5G wireless, next-generation ADAS and the Industrial Internet of Things.
The ADRV9009 is a highly integrated radio frequency (RF), agile transceiver that provides dual transmitters and receivers, integrated frequency synthesizers, and digital signal processing. The IC offers a diverse combination of high performance and low power consumption to meet the requirements of 3G, 4G, and 5G macro cellular time division duplex (TDD) base station applications.
The SDR-LW 3980 is ideal for building a range of advanced research applications, including standalone 5G or 802.11 device emulation, development of media access control (MAC) algorithms, multiple-input multiple-output (MIMO) systems, heterogeneous networks, and heterogeneous networks 5G transmission, RF anti-compression sampling, spectral remote sensing, cognitive radio, beamforming and direction finding.
|Xilinx Zynq UltraScale+ ZU11EG
|Quad-core ARM® Cortex-A53
|Dual-core Cortex-R5 real-time processors
|Mali-400 MP2 graphics processing
|653k System Logic Cells
|PS 4 GByte DDR4(x64) (with ECC)
|PL 2 GByte DDR4(x32)
|Number of transmit channels
|The number of receive channels
|Observe the number of receive channels
|Receive the maximum bandwidth
|Transmit maximum bandwidth
|Observe the maximum bandwidth received
|RX ADC bits
|TX DAC digits
|Multi-slice phase synchronization
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